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CS5111
CS5111
1.4A Switching Regulator with 5V, 100mA Linear Regulator with Watchdog, RESET and ENABLE
Description
The CS5111 is a dual output power supply integrated circuit. It contains a 5V 2%, 100mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4A current mode PWM switching regulator. The 5V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2V (typical) dropout voltage at maximum load current. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1V. During power up, or if the output voltage shifts below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4A output power switch with anti-saturation control. The switching regulator can be configured in a variety of topologies. The CS5111 is load dump capable and has protection circuitry which includes overvoltage shutdown, current limit on the linear and switcher outputs, and an overtemperature limiter.
Features
s Linear Regulator 5V 2% @ 100mA s Switching Regulator 1.4A Peak Internal Switch 120kHz Maximum Switching Frequency 5V to 26V Operating Supply Range s Smart Functions Watchdog RESET ENABLE s Protection Overvoltage Overtemperature Current Limit s 54V Peak Transient Capability
Block Diagram
VFB1 VFB2 SELECT COMP IBIAS COSC Oscillator Multiplexer + Switcher Error Amplifier
COMP
VIN Logic Base Drive + Gnd VSW 1.4A
Package Option
24 Lead SO Wide (Internally Fused Leads)
VIN NC
1
Current Sense Amplifier
ENABLE VREG VLIN IBIAS Gnd Gnd Gnd Gnd RESET CDelay WDI COSC
+ Switcher Shutdown ENABLE
VREG Over Voltage + Linear Error Amplifier
NC VSW Gnd
VLIN Current Limit Over Temperature
Gnd Gnd Gnd VFB1 VFB2
1.25V Bandgap Reference
CDELAY WDI
RESET & Watchdog Timer
RESET
SELECT COMP
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 12/28/98
1
A
(R)
Company
CS5111
Absolute Maximum Ratings Logic Inputs/Outputs ( ENABLE , SELECT, WDI, RESET ) ................................................................................-0.3V to VLIN VLIN ................................................................................................................................................................................-0.3V to 10V VIN, VREG: DC Input Voltage .................................................................................................................................................-0.3V to 26V Peak Transient Voltage (40V Load Dump @ 14V VIN)....................................................................................-0.3V to 54V VSW Peak Transient Voltage .....................................................................................................................................................54V COSC, CDelay, COMP,VFB1, VFB2 ..................................................................................................................................-0.3V to VLIN Power Dissipation.............................................................................................................................................Internally Limited VLIN Output Current ........................................................................................................................................Internally Limited VSW Output Current .........................................................................................................................................Internally Limited RESET Output Sink Current ..................................................................................................................................................5mA ESD Susceptibility (Human Body Model)..............................................................................................................................2kV ESD Susceptibility (Machine Model).....................................................................................................................................200V Storage Temperature ...................................................................................................................................................-65 to 150C Lead Temperature Soldering: Reflow (SMD styles only) ..........................................60 sec. max above 183C, 230C peak
Electrical Characteristics: 5V VIN 26V and -40C TJ 150C, COUT = 100F (ESR8), CDelay = 0.1F, RBIAS = 64.9k, COSC = 390 pF, CCOMP = 0.1F unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s General IIN Off Current IIN On Current IREG Current Thermal Limit 6.6V VIN 26V, ISW = 0A 6.6V VIN 26V, ISW = 1.4A ILIN = 100mA, 6.6V VREG 26V Guaranteed by design 160 30 2.0 70 6 210 mA mA mA C
s 5V Regulator Section VLIN Output Voltage Dropout Voltage Overvoltage Shutdown Line Regulation Load Regulation Current Limit DC Ripple Rejection
6.6V VREG 26V, 1mA ILIN 100mA (VREG - VLIN) @ ILIN = 100mA
4.9 30
5.0 1.2 34 5 5
5.1 1.5 38 25 25
V V V mV mV mA dB
6.6V VREG 26V, ILIN = 5mA VREG = 19V, 1mA ILIN 100mA 6.6V VREG 26V 14V VREG 24V 120 60
75
s RESET Section Low Threshold (VRTL) High Threshold (VRTH) Hysteresis Active High Active Low Delay Power On Delay
VLIN Decreasing VLIN Increasing VRTH - VRTL VLIN > VRTH, IRESET = -25A VLIN = 1V, 10k pullup from RESET to VLIN VLIN = 4V, IRESET = 1mA Invalid WDI VLIN crossing VRTH
4.05 4.20 140 VLIN - 0.5
4.25 4.45 190
4.45 4.70 240 0.4 0.7
V V mV V V V ms ms
6.25 6.25
8.78
11.0
2
CS5111
Electrical Characteristics: 5V VIN 26V and -40C TJ 150C, COUT=100F(ESR 8), CDelay = 0.1F, RBIAS = 64.9k, COSC = 390 pF, CCOMP = 0.1F unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Watchdog Input (WDI) VIH VIL Hysteresis Pull-Up Resistor Low Threshold Floating Input Voltage WDI Pulse Width
Peak WDI needed to activate RESET 0.8 Note 1 WDI=0V 25 20 6.25 3.5 50 50 8.78
2.0
V V mV
100 11.0 5
k ms V s
s Switcher Section Minimum Operating Input Voltage Switching Frequency Switch Saturation Voltage Output Current Limit Max Switching Frequency VFB1 Regulation Voltage VFB2 Regulation Voltage VFB1, VFB2 Input Current Oscillator Charge Current Oscillator Discharge Current CDelay Charge Current Switcher Max Duty Cycle Current Sense Amp Gain Error Amp DC Gain Error Amp Transconductance VFB1 = VFB2 = 5V COSC = 0V COSC = 4V CDelay = 0V VSW = 5V with 50 load, VFB1 = VFB2 = 1V ISW = 2.3A 35 270 35 72 40 320 40 85 7 67 2700 VSW = 7.5V with 50 load, Refer to Figure 1d. Refer to Figure 1d. ISW = 1.4A 80 0.7 1.4 120 1.206 1.206 1.25 1.25 95 1.1
5.0 110 1.6 2.5
V kHz V A kHz
1.294 1.294 1 45 370 45 95
V V A A A A %
dB A/V
s ENABLE Input VIL VIH Hysteresis Input Impedance
0.8
1.24 1.30 60 2.0 40
V V mV k
10
20
s Select Input VIL (Selects VFB1) VIH (Selects VFB2) SELECT Pull-Up Floating Input Voltage
4.9 VLIN 5.1 4.9 VLIN 5.1 SELECT = 0V
0.8 10 3.5
1.25 1.25 24 4.5 2.0 50
V V k V
Note 1: Guaranteed by Design, not 100% tested in production.
3
CS5111
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
24 Lead SO Wide 1 2, 3 4 5,6,7,8,17,18,19,20 9 10 11 12 13 14 15 16 21 22 23 24 VIN NC VSW Gnd VFB1 VFB2 SELECT COMP COSC WDI CDelay RESET IBIAS VLIN VREG ENABLE Supply Voltage. No connection. Collector of NPN power switch for switching regulator section. Connected to the heat removing leads. Feedback input voltage 1 (referenced to 1.25V) Feedback input voltage 2 (referenced to 1.25V) Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to Gnd to select VFB1. Output of the transconductance error amplifier. A capacitor connected to Gnd sets the switching frequency. Refer to Figure 1d. Watchdog input. Active on falling edge. A capacitor connected to Gnd sets the Power On Reset and Watchdog time. RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued. A resistor connected to Gnd sets internal bias currents as well as the COSC and CDelay charge currents. Regulated 5V output from the linear regulator section. Input voltage to the linear regulator and the internal supply circuitry. Logic level input to shut down the switching regulator.
Typical Performance Characteristics
4.5mA 0A
-10mA
IREG - ILIN
IIN
20mA 40mA 60mA 80mA 100mA
4.0mA
-20mA
-30mA
3.5mA 0A
-40mA 0A 0.5A 1.0A 1.5A 2.0A
ILIN
ISW
Figure 1a. 5V Regulator Bias Current vs. Load Current.
1.4V 1.2V 1.0V
Figure 1b. Supply Current vs. Switch Current.
180 160
Frequency (kHz)
140 120 100 80 60 40 20
VSW
0.8V 0.6V 0.4V 0.2V 0.0V 0A 0.5A 1.0A 1.5A 2.0A
0
0
500
1000
1500
2000
2500
3000
ISW
COSC (pF)
Figure 1c. Switch Saturation Voltage.
Figure 1d. Oscillator Frequency (kHz) vs. COSC (pF), assuming RBIAS = 64.9k.
4
CS5111
Circuit Description
VREG Over Voltage + 1.25V Current Limit Over Temperature IBIAS RBIAS 64.9k Cdelay WDI Bandgap Reference RESET & Watchdog Timer
Figure 2. Block diagram of 5V linear regulator portion of the CS5111.
R1 Linear Error Amplifier
Q2 Q1 Q3 R2 R3 R4 R5 RESET VLIN COUT = 100F ESR < 8
5V Linear Regulator
The 5V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5V linear regulator circuitry is shown in Figure 2. When an unregulated voltage greater than 6.6V is applied to the VREG input, a 5V regulated DC voltage will be present at VLIN. For proper operation of the 5V linear regulator, the IBIAS lead must have a 64.9k pull down resistor to ground. A 100F or larger capacitor with an ESR <8 must be connected between VLIN and ground. To operate the 5V linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the VREG lead. As the voltage at the VREG input is increased, Q1 is turned on. Q1 provides base drive for Q2 which in turn provides base current for Q3. As Q3 is turned on, the output voltage, VLIN, begins to rise as Q3's output current charges the output capacitor, COUT. Once VLIN rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to Q1. The error amplifier monitors the scaled output voltage via an internal voltage divider, R2 through R5, and compares it to the bandgap voltage reference. The error amplifier output or error signal is an output current equal to the error amplifier's input differential voltage times the transconductance of the amplifier. Therefore, the error amplifier varies the base current to Q1, which provides bias to Q2 and Q3, based on the difference between the reference voltage and the scaled VLIN output voltage.
Control Functions
Using CDelay = 0.1F and RBIAS = 64.9k gives a time ranging from 6.25ms to 11ms assuming ideal components. Based on this, the software must be written so that the watchdog arrives at least every 6.25ms. In practice, the tolerance of CDelay and RBIAS must be taken into account when calculating the minimum watchdog time (tWDI).
VREG
RESET
WDI
VLIN tPOR Normal Operation
Figure 3. Timing diagram for normal regulator operation.
VREG
50% Duty Cycle
RESET
WDI
The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see Figure 3). The watchdog time is given by: tWDI = 1.353 x CDelay RBIAS 5
VLIN tPOR A
A: Watchdog waiting for low-going transition on WDI
B
B: RESET stays low for tWDI time.
Figure 4. Timing diagram when WDI fails to appear within the preset time interval, tWDI.
CS5111
Circuit Description: continued If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. The nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in Figure 4. The RESET signal frequency is given by: 1 fRESET = 2(tWDI) The Power On Reset (POR) and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. After VLIN rises above the minimum specified value, RESET remains low for a fixed period tPOR as shown in Figure 5. The POR delay (tPOR) is given by: tPOR = 1.353 x CDelay RBIAS The switching regulator begins operation when VREG and VIN are raised above 5 volts. VREG is required since the switching supply's control circuitry is powered through VLIN. VIN supplies the base drive to the switcher output transistor. The output transistor turns on when the oscillator starts to charge the capacitor on COSC. The output current will develop a voltage drop across the internal sense resistor (RS). This voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. The error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (VFB1 or VFB2) and the internal bandgap voltage reference. Once the current sense amplifier output exceeds the error amplifier's output voltage, the output transistor is turned off. The energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. The output transistor is turned back on at the next rising edge of the oscillator. On a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. Figure 7 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode. NOTES: 1. Refer to Figure 1d to determine oscillator frequency. 2. The switching regulator can be disabled by providing a logic high at the ENABLE input. 3. The boost output voltage can be controlled dynamically by the feedback select input. If select is open, VFB2 is selected. If select is low, then VFB1 is selected.
VLIN 4.45V 4.25V
RESET
VRLO VRPEAK tPOR
Figure 5a. The power on reset time interval (tPOR) begins when VLIN rises above 4.45V (typical).
VLIN 5V 4.25V
Protection Circuitry
RESET 5V
tPOR
Figure 5b. RESET signal is issued whenever VLIN falls below 4.25V (typical).
Current Mode PWM Switching Circuitry
The current mode PWM switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4A output power switch with antisaturation control. The switching regulator and external components, connected in a boost configuration, are shown in Figure 6.
If the input voltage at VREG is increased above the overvoltage threshold, the drive to the linear and switcher output transistors is shut off. Therefore, VLIN is disabled and VSW can not be pulled low. The current out of VLIN is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0V to regulation. Also, the current into VSW is sensed in order to provide the current limit function in the switcher output transistor. If the die temperature is increased above 160C, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. Therefore, VLIN will decrease with increasing die temperature above 160C. Since the switcher control circuitry is powered through VLIN, the switcher performance, including current limit, will be affected by the decrease in VLIN.
6
CS5111
Circuit Description: continued
VIN VLIN VOUT IBIAS RBIAS 64.9k COSC Oscillator ENABLE VREG +
COMP
VSW Logic Current Sense Amplifier Base Drive + RS Gnd 1.4A
COUT
Over Voltage COMP Switcher Error Amplifier VFB1 + SELECT Multiplexer VFB2
Figure 6: Block diagram of the 1.4A current mode control switching regulator portion of the CS5111 in a boost configuration.
Application Notes
Design Procedure for Boost Topology
This section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode. Step 1 Determine the output power required by the load. POUT = IOUTVOUT
(1)
Step 2 Choose COSC based on the target oscillator frequency with an external resistor value, RBIAS = 64.9k. (See Figure 1d).
VSW VOUT
VIN
VSAT 0 ISW IPeak t
0 ID IPeak
t
0
t
Figure 7: Voltage and current waveforms for boost topology in CS5111.
-
Switcher Shutdown 1.25V
Bandgap Reference R1 R2 R3
Step 3 Next select the output voltage feedback sense resistor divider as follows (Figure 8). For VFB1 active, choose a value for R1 and then solve for REQ where: REQ = R1 VOUT -1 VFB1
.
(3a)
VOUT R1
For VFB2 active, find: VFB1 = VOUT
(
REQ R1 + REQ
)
REQ
, (3b)
{
VFB1 VR2 R2 VFB2 R3
and then calculate R2 where: VR2 IR2 VFB1 - VFB2 VFB1/REQ . (3c)
Figure 8. Feedback sense resistor divider connected between VOUT and ground.
R2 =
=
Then find R3, where:
R3 = REQ - R2.
(3d)
7
CS5111
Application Notes: continued Step 4 Determine the maximum on time at the minimum oscillator frequency and VIN. For discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. Since the current through the inductor cannot change instantaneously and the inductance is constant, a volt-second balance exists between the on time and off time. The voltage across the inductor during the on cycle is VIN and the voltage across the inductor during the off cycle is VOUT - VIN. Therefore: VINton = (VOUT -VIN)toff where the maximum on time is: ton(max) (4a) overall loop gain is 0dB at the crossover frequency, fCO. In addition, the gain slope should be -20dB/decade at the crossover frequency. The low frequency gain of the modulator (i.e. error amplifier output to output voltage) is: VOUT VEA where Ipk(max) = = Ipk(max) VEA(max)
RLoad L f , 2
(8a)
(2.4V)/(7) VEA(max)/GCSA = =2.3A. 150m RS
[
1-
VIN(min) VOUT(max)
][
1 fSW(min)
]
The VOUT/VEA transfer function has a pole at: . (4b) fp = 1/(RLoadCOUT) , and a zero due to the output capacitor's ESR at: fz = 1/(2ESR COUT). (8c) (8b)
Step 5 Calculate the maximum inductance allowed for discontinuous operation: L(max) = fSW(min) VIN2(min) ton2(max) 2 POUT/ (5)
Since the error amplifier reference voltage is 1.25V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is: 1.25V . VOUT The error amplifier in the CS5111 is an operational transconductance amplifier (OTA), with a gain given by: GOTA = gmZOUT where: gm = IOUT . VIN (8d) (8e)
where = efficiency. Usually = 0.75 is a good starting point. The IC's power dissipation should be calculated after the peak current has been determined in Step 6. If the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current. Step 6 Determine the peak inductor current at the minimum inductance, minimum VIN and maximum on time to make sure the inductor current doesn't exceed 1.4A. Ipk = Step 7 Determine the minimum output capacitance and maximum ESR based on the allowable output voltage ripple. COUT(min) = ESR(min) = Ipk 8fVripple Vripple Ipk (7a) (7b) VIN(min) ton(max) L(min) (6)
For the CS5111, gm = 2700A/V typical. One possible error amplifier compensation scheme is shown in Figure 9. This gives the error amplifier a gain plot as shown in Figure 10. For the error amplifier gain shown in Figure 10, a low frequency pole is generated by the error amplifier output impedance and C1. This is shown by the line AB with a 20dB/decade slope in Figure 12. The slope changes to zero at point B due to the zero at: fz = 1/(2R4C1).
VOUT R1 1.25V VFB1 M R2 R3 VFB2 U - X Error Amplifier C1 R4 C2 +
(8f)
In practice, it is normally necessary to use a larger capacitance value to obtain a low ESR. By placing capacitors in parallel, the equivalent ESR can be reduced. Step 8 Compensate the feedback loop to guarantee stability under all operating conditions. To do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the 8
SELECT
Figure 9. RC network used to compensate the error amplifier (OTA).
CS5111
Application Notes: continued
VIN
Pole due to error amplifier output impedance and C1 A fz = 1/2R4C1 fP = 1/R4C2 G +G B
error amplifier gain
VOUT = 18V, Select > 2V VOUT = 16V, Select < 0.8V
VIN NC NC
ENABLE VREG VLIN IBIAS Gnd Gnd Gnd Gnd RESET CDelay WDI COSC COSC 390pF Cdelay 0.1F
MICROPROCESSOR
C -20dB/dec
L=33H VSW (2) Gnd Gnd R1 100k
5V 100F ESR<8 RBIAS = 64.9k
Gain (dB)
COUT 88F
CS-5111
fP = 1/ RLoadCOUT fCO 0
Gnd Gnd
R2
modulator gain + feedback resistor divider attenuation
946 7.5k CCOMP 0.33F
(1)
VFB1 VFB2 SELECT COMP
R3
-G
fz = 1/2 ESR COUT
Figure 10. Bode plot of error amplifier (OTA) gain and modulator gain added to the feedback resistor divider attenuation.
Figure 11. A typical application diagram with external components configured in a boost topology.
A pole at point C: fp = 1/(R4C2), (8g) Step 9 Finally the watchdog timer period and Power on Reset time is determined by: tDelay = 1.353 x CDelayRBIAS. (9)
offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 11, to roll the gain off at a relatively low frequency.
Linear Regulator Output Current vs. Input Voltage
100
100
75
75
ILIN (mA)
ILIN (mA)
50
JA = 55C/W VIN = 14V Max Total Power = 1.18W
50
JA = 35C/W VIN = 14V Max Total Power = 1.86W
25
25
0 0 5 10 15 20 25 30
0 0 5 10 15 20 25 30
VREG (V)
VREG (V)
Figure 12: The shaded area shows the safe operating area of the CS5111 as a function of ILIN, VREG, and JA. Refer to the table below for typical loads and voltages.
VREG (V)
VIN (V)
ILIN (mA)
Linear Power Dissipation (W)
Worst Case Switcher Power Available (JA = 55C/W) (W)
Worst Case Switcher Power Available (JA = 35C/W) (W)
20 20 20 20 25 25 25 25
14 14 14 14 14 14 14 14
25 50 75 100 25 50 75 100
0.44 0.83 1.22 1.60 0.60 1.11 1.62 2.14 9
0.74 0.35 * * 0.58 0.07 * *
1.42 1.03 0.64 0.26 1.26 0.75 0.24 *
* Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit.
CS5111
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 24 Lead SO Wide
(internally fused leads)
Metric Max Min 15.60 15.20
English Max Min .614 .598
Thermal Data RJC typ typ RJA
24 Lead SO Wide 9 55
C/W C/W
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299) 7.40 (.291)
10.65 (.419) 10.00 (.394)
0.51 (.020) 0.33 (.013)
1.27 (.050) BSC
2.49 (.098) 2.24 (.088)
2.65 (.104) 2.35 (.093)
1.27 (.050) 0.40 (.016)
REF: JEDEC MS-013
0.32 (.013) 0.23 (.009) D 0.30 (.012) 0.10 (.004)
Ordering Information
Part Number CS5111YDWF24 CS5111YDWFR24
Description 24 Lead SO Wide (internally fused leads) 24 Lead SO Wide (internally fused leads) (tape & reel) 10
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
(c) 1999 Cherry Semiconductor Corporation
Rev. 12/28/98

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